Because of the great demand for a thin display, the technology of a plasma display panel has been developed and substantially advanced recently. A plasma display panel comprises a plurality of data electrodes and a plurality of scanning lines arranged perpendicular to the data electrodes to form a plurality of cells at the intersections. The cells are electronically driven to emit light, according to video signals corresponding to the predetermined gray level of the cells.
In FIG. 1, a frame of the video signal is divided into four (4) successive subfields SF1-SF4. Each subfield is further apportioned into successive periods of reset (Rc), address (Wc), sustain (Ic) and erase (E). In the reset period (Rc) all cells are set to an initial state, either ON or OFF state. In the address period (Wc) each cell is set to either ON or OFF according to the corresponding image data. In the sustain period (Ic), the ON or OFF state of each cell is maintained. In the erase period (E), the cells in the ON state are switched to OFF. The gray level of the emitted light of each cell is determined by the number and the duration of subfields set to ON in the frame. The duration of the sustain period of a subfield is proportional to the brightness generated from that specific subfield. For example, when a frame has four subfields, the duration of the sustain period of which is set to 1:2:4:8, the brightness generated from the respective subfields is also weighted 1:2:4:8. As a result, sixteen (16) gray levels can be presented in the frame by each cell. Likewise, for a frame with eight (8) subfields, 256 gray levels can be displayed. Thus, a PDP driven by a video signal having N subfields per frame is capable of displaying a video image with 2N gray levels.
A disadvantage of the aforementioned method is that each cell is reset at the beginning of each subfield and addressed in the following address period of the same subfield, causing high numbers of switching operations and consequently resulting in high switching loss and heat generation of the addressing ICs. The addressing ICs are high speed digital integrated circuits performing addressing operations. Another disadvantage is that a display of dynamic false contour occurs while displaying a moving image.
In FIG. 2, a reset period (Rc) exists only at a beginning of a frame, and an erase period exists only at an end of a frame. Since there is no reset or erase period between subfields in a frame, once a cell is addressed, i.e., set to 1, and switched ON in the selective-write mode, or alternatively switched OFF in the selective-erase mode, it will remain in the same state throughout the frame. Therefore, each cell is addressed at most once in one frame and the switching loss and heat generation of addressing ICs is reduced. However, additional reduction in the switching and switching loss is desired.